This invention relates generally to programming antifuses in semiconductor circuits, and, more particularly, to a method and apparatus for programming antifuses with a sufficiently high voltage to provide a consistently low resistance of the programmed antifuse without overstressing semiconduct or devices in the integrated circuit.
Antifuses are a common component in conventional integrated circuits. An antifuse is a circuit element that is normally open circuited until it is programmed, at which point the antifuse assumes a relatively low resistance. Antifuses are commonly used to selectively enable certain features of integrated circuits and to perform back end repairs of integrated circuits, i.e., repairs after the integrated circuit has been packaged. Back end repairs of integrated circuits are typically accomplished by xe2x80x9cblowingxe2x80x9d antifuses to signal defective portions of the integrated circuit that they should be replaced with redundant circuits. For example, a defective row of memory cells in the array of a dynamic random access memory can be replaced with a redundant row of cells provided for that purpose.
Conventional antifuses are similar in construction to capacitors in that they include a pair of conductive plates separated from each other by a dielectric or insulator. Antifuses are typically characterized by the nature of the dielectric which may be, for example, oxide, nitride or tantalum pentoxide. Antifuses are programmed or xe2x80x9cblownxe2x80x9d by applying a differential voltage between the plates that is sufficient to break down the dielectric thereby causing the plates to contact each other. Typically this relatively high programming voltage is applied to the chip externally through terminals that are normally used for other purposes. For example, in a DRAM, a high voltage may be applied to one of the data bit terminals after the integrated circuit has been placed in a programming mode by, for example, applying a predetermined combination of bits to other terminals of the integrated circuit.
Although conventional antifuses as described above have worked well in many applications, they nevertheless have several shortcomings, particularly when used in higher density integrated circuits. In particular, the programmed resistance of antifuses may vary over a considerable range, and the programmed resistance is often far higher than is desired. For example, sometimes the programmed resistance is high enough that circuitry connected to the antifuse mistakenly determines that the antifuse is open circuited. It is generally known that programming antifuses with a higher voltage will both lower the programmed resistance and provide a more uniform resistance. However, the magnitude of the programming voltage that can be applied to antifuses is severely limited by the presence of other circuitry in the integrated circuit. In particular, since the terminals on which the programming voltage is applied are typically used for other functions, excessive programming voltages can easily break down the gate oxide layers of MOSFETs connected to such terminals thereby making such transistors defective. If the programming voltage was coupled to the integrated circuit substrate, excessive voltages could still be coupled across the gate oxide layers of MOSFETs, even though the programming voltage was not applied directly to the gates of the transistors. The problem of programming voltages breaking down the gate oxide layer of MOSFETs is exacerbated by the wide range of operating voltages of typical integrated circuits. For example, recent integrated circuits are capable of operating with a supply voltage of 3.3 volts in order to minimize power consumption, but they must still be able to operate with a commonly used supply voltage of 5 volts.
A plurality of conventional antifuse circuits 10a,b,c . . . n are shown in FIG. 1. The antifuse circuits 10 are part of an integrated circuit 12, such as a memory device, and are programmed to control or affect the operation of the integrated circuit 12, as explained above. Only one 10c of the antifuse circuits 10 is illustrated in detail in FIG. 1, it being understood that the structure and operation of the other antifuse circuits 10a,b . . . n are identical. The antifuse circuit 10c receives an operating voltage Vcc at a source of a PMOS transistor 14. The PMOS transistor 14 is coupled through two PMOS transistors 20, 22 in parallel to an input of an inverter 26. The input of the inverter 26 is coupled to a ground through two series-connected NMOS transistors 30, 32. The gates of the PMOS transistor 20 and the NMOS transistor 30 receive a read fuse signal RDFUS* from an external source. The RDFUS* signal is an active low signal that is normally high to render the PMOS transistor 20 non-conductive and the NMOS transistor 30 conductive. A gate of an NMOS transistor 46 receives a signal DVC2F, which is slightly greater than one-half Vcc, thereby maintaining the NMOS transistor 46 in a conductive state. Similarly, a gate of an NMOS transistor 48 receives a boosted voltage Vccp, which has a magnitude exceeding the magnitude of Vcc, and maintains the NMOS transistor 48 in a conductive state.
A junction between the NMOS transistors 46, 48 receives a bank select signal BSEL* through an NMOS transistor 50 having a gate receiving a fuse add signal FA. A second terminal of the antifuse 40 receives a common ground signal CGND, and it may be selectively coupled to ground potential by an NMOS transistor 74. A CGND terminal 52, as well as the CGND terminals of the other antifuse circuits 10, are normally coupled through a conductor 54 to a bond or programming pad 56 formed in the integrated circuit by conventional means.
The programming voltage may be applied directly to the pad 56 to program the antifuse 40 prior to packaging the integrated circuit 12. Alternatively, the pad 56 may be coupled to an external terminal 58 by a bond wire 60, as is well known in the art. In such case, the antifuse 40 may be programmed after packaging, and the external terminal 58 may be used to couple other signals to the integrated circuit 12, as is well known in the art. For example, the terminal 58 can be used to couple an address signal to an address buffer (not shown) in a memory device. As is well known in the art, additional bond pads, such as the bond pad 55, are formed in the integrated circuit 12. The bond pad 55 is coupled to an external terminal 57 by a bond wire 59 so that signals, such as data signals in the case of a memory device, can be coupled to circuits (not shown) in the integrated circuit 12.
If the bond wire 60 is used, the antifuse circuit 10 preferably includes a pass gate 78 coupled between the CGND terminal 52 and the antifuse 40 to isolate the CGND terminal 52 from the antifuse 40 during normal operation of the integrated circuit 12 but to couple the CGND terminal 52 to the antifuse 40 during programming. The pass gate 78 is controlled by the BSEL* signal directly and through an inverter 80. The BSEL* is normally high, but is brought low when the antifuse 40 is to be programmed, thereby closing to pass gate to couple the CGND terminal to the antifuse 40.
In a similar manner, the RDFUS*, DVC2F, BSEL*, FA and CGND signals may be applied through respective externally accessible terminals (not shown) that are used for some other purpose during normal operation, such as, in the case of a memory device, the transfer of data.
The antifuse circuit 10c is preferably programmed during manufacture of the integrated circuit 12 in which it is formed. In the case of a memory device, the antifuse circuit 10c may be programmed after undergoing a test procedure. During programming, the BSEL* signal is brought low and a programming signal of about 10 volts is applied to the external terminal 58, thereby closing the pass gate 78 and coupling the 10 volt input to antifuse 40. Selected antifuses, such as the antifuse 40, are blown when the fuse add signal FA is brought high to render the NMOS transistor 50 conductive to allow current flow through the antifuse 40 and the NMOS transistors 48, 50. The current breaks down the dielectric layer in the antifuse 40. If the antifuse 40 is to remain unblown, the fuse add signal FA is kept low such that the NMOS transistor 50 prevents current from flowing through the antifuse 40. The signals BSEL*, FA, and CGND are used only to program antifuse circuits 10, although, as previously stated, the external terminals thorough which these signals may be applied are used for other purposes during normal operation. During operation of the integrated circuit containing the antifuse circuit 10c, the fuse add signal FA is held low to render the NMOS transistor 50 and the pass gate 78 non-conductive.
The antifuse circuit 10c indicates whether the antifuse 40 is blown or unblown with a signal at an output of the inverter 26. When the conductive state of the antifuse 40 is to be read, the RDFUS* signal is driven to an active low state, thereby causing a bias circuit formed by the transistors 14, 20 to apply a bias voltage to a first terminal of an antifuse 40 through two NMOS transistors 46, 48. Additionally, the CGND terminal must be coupled to ground. For this purpose, the pulsed-low RDFUS* signal is applied to the gate of the NMOS transistor 74 thereby turning the transistor 74 ON. The transistor 74 then couples the common ground terminal CGND to ground. If the antifuse 40 is unblown and thus remains non-conductive, the antifuse 40 is charged to the supply voltage Vcc. This rise in voltage on the terminal of the antifuse 40 is coupled to the input of the inverter 26 because the NMOS transistors 46, 48 are ON. As the voltage rises above a threshold voltage of the inverter 26, the inverter 26 outputs a low to indicate that the antifuse 40 is unblown. The low at the output of the inverter turns on the PMOS transistor 22 to couple a high to the input of the inverter 26, thereby latching the output of the inverter 26 low. The output of the inverter 26 will thus remain low when the low RDFUS* pulse terminates to turn the PMOS transistor 20 OFF.
If the antifuse 40 is blown such that it conducts current, then the input of the inverter 26 is held at substantially zero volts despite Vcc being coupled to the antifuse 40 though the transistors 14, 20, 46, 48 when the RDFUS* signal pulses low. The inverter 26 then outputs a high to indicate the blown state of the antifuse 40. The high at the output of the inverter turns on the NMOS transistor 32. When the low RDFUS* pulse terminates to turn ON the NMOS transistor 30, the input of the inverter 26 is pulled to ground through the transistors 30, 32, thereby latching the output of the inverter 26 high.
The magnitude of the negative programming voltage applied to the antifuse 40 must be sufficiently large to adequately blow the antifuse 40 so that it consistently has a low resistance value. In practice, however, the resistance values of blown antifuses 40 vary considerably from one fuse to another. This is problematic because an antifuse 40 that has not been sufficiently xe2x80x9cblownxe2x80x9d may be interpreted as being an open circuit, and may thus cause improper operation of other circuitry whose operation depends on the state of the antifuse 40. One way to more consistently program the antifuse 40 is to increase the voltage applied to the antifuse during programming by making the negative voltage applied to the CGND terminal more negative. This approach is limited, however, because the use of larger voltages could easily overstress the NMOS transistor 74. Eliminating the NMOS transistor 74 would conceivably permit the use of negative programming voltages having a larger magnitude, but then the CGND terminal would not be coupled to ground thereby preventing the state of the antifuse 40 from being read. Also, if the external terminal 58 is used to couple signals to other semiconductor devices in the integrated circuit 12, the programming voltage could also overstress these other devices.
There is therefore a need for a circuit and method to allow larger programming voltages to be applied to antifuses in an integrated circuit in a manner that does not overstress semiconductor devices in the integrated circuit.
A method and apparatus for programming an antifuse includes a conductive path extending between a terminal of the antifuse and a programming pad formed on a semiconductor substrate. The conductive path, including the programming pad, is isolated from the semiconductor substrate and all semiconductor devices fabricated on the semiconductor substrate. As a result, a programming voltage having a relatively large magnitude can be applied to the antifuse without any significant risk of overstressing the semiconductor devices. After the antifuse has been programmed, the programming pad is coupled to a reference voltage, such as ground potential, so that the conductive state of the antifuse can be read.